1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to a method for fabricating an array of DRAM cells with closely spaced capacitors having reduced parasitic capacitance between adjacent capacitors, and DRAM embedded in integrated circuits.
2. Description of the Prior Art
Dynamic random access memory (DRAM) circuits (devices) are used extensively in the electronics industry, and more particularly in the computer industry for storing data in binary form (1s and 0s) as charge on a storage capacitor. These DRAM devices are made on semiconductor substrates (or wafers) and then the substrates are diced to form the individual DRAM circuits (or chips). Each DRAM circuit (chip) consists in part of an array of individual memory cells that store binary data (bits) as electrical charge on the storage capacitors. Further, the information is stored and retrieved from the storage capacitors by means of switching on or off a single access transistor (via word lines) in each memory cell using peripheral address circuits, while the charge stored on the capacitors is sensed via bit lines and by read/write circuits formed on the peripheral circuits of the DRAM chip.
The access transistor for the DRAM device is usually a field effect transistor (FET), and the single capacitor in each cell is formed either in the semiconductor substrate as a trench capacitor, or is built over the FET in the cell area as a stacked capacitor. To maintain a reasonable DRAM chip size and improved circuit performance, it is necessary to further reduce the area occupied by the individual cells on the DRAM chip, and to move the adjacent capacitors on memory cells closer together. Unfortunately, as the cell size decreases, it becomes increasingly more difficult to fabricate stacked or trench storage capacitors with sufficient capacitance to store the necessary charge to provide an acceptable signal-to-noise level for the read circuits (sense amplifiers) to detect. The reduced charge also requires more frequent refresh cycles that periodically restore the charge on these volatile storage cells. This increase in refresh cycles further reduces the performance (speed) of the DRAM circuit. As cell density increases and cell area decreases, it is also necessary to make the capacitors closer together. This results in increased parasitic capacitance between adjacent capacitors and can disturb the data retention (charge) on the capacitor.
Since the capacitor area is limited to the cell size in order to accommodate the multitude of cells on the DRAM chip, it is necessary to explore alternative methods for increasing the capacitance while decreasing the lateral area that the capacitor occupies on the substrate surface. In recent years the method of choice is to build stacked capacitors in the vertical direction over the access transistors within each cell area to increase the capacitance of the individual capacitors by increasing the capacitor area in the vertical direction. However, when these vertical stacked capacitors are formed by making bottom electrodes in recesses in an insulating layer (having dielectric constant k), the increase in parasitic capacitance between adjacent capacitors can adversely affect, the data retention.
The unwanted parasitic capacitance Cp (Cp=kA/d) between capacitors increases because of their close proximity (decreasing spacing d), and because the effective area A also increases between adjacent capacitors.
Several methods have been reported that increase the capacitance of the individual capacitors, but do not address the problem associated with the parasitic capacitance Cp due to the close proximity of adjacent capacitors. For example, in U.S. Pat. No. 5,811,331 to Ying et al., a method is taught for making cylindrical capacitors with improved void-free insulation and better photolithographic overlay tolerances. In U.S. Pat. No. 5,851,877 to Ho et al., a method of making crown-shaped capacitors is described in which the formation of a polymer residue on the sidewalls of the bottom electrodes during etching is utilized as an etch mask. In U.S. Pat. No. 5,858,829 to Chen, a method is described for making cylindrical-shaped capacitors self-aligned to bit lines formed from electrically conducting sidewall spacers (split bit line) that reduces cell area. Still another method for reducing RC time constant by reducing the capacitance C is taught in U.S. Pat. No. 5,858,869 to Chen et al., in which, a low-dielectric-constant (low-k) oxide and polymer are used between metal lines (interconnections).
Although there has been considerable work done to increase the capacitor area on these miniature stacked capacitors, there is still a need to fabricate an array of DRAM cells with minimum parasitic capacitance between adjacent capacitors. This will become exceptionally important as the cell area decreases on future gigabit DRAM circuits anticipated for production after the year 2000.
A principal object of the present invention is to fabricate capacitor-over-bit line (COB) DRAM cells with closely spaced capacitors having reduced parasitic capacitance between closely spaced capacitors.
Another object of this invention is to utilize an insulator having a low dielectric constant (low-k) between the closely spaced capacitors on adjacent memory cells to reduce the parasitic capacitance and to improve the charge retention time on the capacitors.
Still another objective of this invention is to provide a very manufacturable process that allows openings to be etched selectively in the low-k insulator for forming the DRAM capacitors.
The method for making an array of closely spaced stacked capacitors with reduced parasitic capacitance between adjacent capacitors on a DRAM device begins by providing a semiconductor substrate. Typically the substrate is a single-crystal silicon substrate doped with a P type conductive dopant, such as boron (B). A relatively thick Field OXide (FOX) is formed surrounding and electrically isolating an array of device areas on the substrate. The field oxide is typically formed using the LOCal Oxidation of Silicon (LOCOS) method, in which a patterned silicon nitride (Si3N4) layer is used to mask the device areas from oxidation while the silicon substrate in the FOX areas is thermally oxidized to the desired thickness. Other field oxide isolations can also be used, such as shallow trench isolation (STI) and the like. A thin gate oxide is then formed in the device areas of the silicon substrate for making semiconductor devices such as field effect transistors (FETs). Typically a polycide (polysilicon/silicide) layer, having a cap layer (optional) consisting of silicon oxide (SiO2) and silicon nitride (Si3N4) thereon, is patterned to form the FET gate electrodes and the interconnecting word lines for the array of memory cells on the DRAM device. The lightly doped source/drain regions are formed adjacent to the FET gate electrodes using ion implantation. A spacer silicon nitride (Si3N4) layer is deposited and anisotropically etched back to form spacers on the sidewalls of the gate electrodes and completes the FETs for the memory cells.
Continuing, a first insulating layer is deposited over the device areas and the FOX areas. The first insulating layer is composed of SiO2 and is deposited by low-pressure chemical vapor deposition (LPCVD). The first insulating layer is then planarized, for example by chemical/mechanical polishing (CMP).
First contact openings for bit lines and for capacitor node contacts are etched in the first insulating layer to the source/drain areas. The first contact openings are etched extending over the gate electrodes, and are etched selectively to the Si3N4 cap layer and sidewall spacers to form self-aligned contacts (SAC). A conductively doped first polysilicon layer is deposited by LPCVD on the first insulating layer and is sufficiently thick to fill the first openings. The first polysilicon layer is etched back to the planar first insulating layer to form bit-line plugs to electrically contact the first source/drain areas, and to concurrently form capacitor node contact plugs to electrically contact the second source/drain areas. A SiO2 second insulating layer is deposited over the first insulating layer and over the bit-line plugs and over the capacitor node contact plugs. Second openings for bit lines are etched in the second insulating layer to the bit-line plugs. Next, a polycide layer, composed of a doped polysilicon layer and a refractory metal silicide layer, is deposited over the second insulating layer. The polycide layer is patterned to form the bit lines over the bit-line plugs.
A third insulating layer, such as SiO2, is deposited over the bit lines and is planarized by chemical-mechanical polishing (CMP). A Si3N4 etch-stop layer is deposited by LPCVD on the third insulating layer. Third openings are etched in the etch-stop layer and in the third and second insulating layers to the capacitor node contact plugs. A second conductively doped polysilicon layer is deposited sufficiently thick to fill the third openings and is chemically-mechanically polished or plasma etched back to the etch-stop layer to form polysilicon plugs in the third openings to the capacitor node contact plugs.
Now, a key feature of this invention is to deposit a fourth insulating layer that has a low dielectric constant (low-k). For example, the low-k material can be a fluorosilicate glass (FSG), a fluorinated amorphous carbon (FLAC), a porous oxide such as nanofoams, and the like. This low-k dielectric material reduces the parasitic capacitance between the closely spaced stacked capacitors and reduces the disturbance of the data retention (electrical charge on the capacitor) of the neighboring DRAM memory cells. Next, an array of recesses is etched in the fourth insulating layer over and to the polysilicon plugs contacting the capacitor node contact plugs. A conformal first conducting layer, such as a doped polysilicon, is deposited and polished back to the surface of the fourth insulating layer to form capacitor bottom electrodes in the recesses. A thin interelectrode dielectric layer having a high dielectric constant (high-k), such as SiO2/Si3N4/SiO2 (ONO), is deposited on the bottom electrodes. A second conducting layer, such as a doped polysilicon, is deposited and patterned to form capacitor top electrodes to complete the array of capacitors. A fifth insulating layer is deposited to electrically insulate the array of capacitors on the DRAM device prior to subsequent processing to complete the DRAM device.